1. Field of the Invention
The present invention relates to charge pump circuits, and in particular, to integrated charge pump circuits providing a regulated output voltage with reduced power requirements for the voltage regulation control.
2. Description of the Related Art
As mobile electronic devices become more sophisticated in terms of features, power consumption becomes increasingly problematic since such increased functionality often requires more power, and as the devices become smaller, battery size becomes more of an issue. Generally, the solution to this has been to use low voltage integrated circuitry, which has improved significantly in recent years. It is now common for many integrated circuit devices to operate with power supply voltages of only two or three volts.
However, low voltage operation, while beneficial in many applications, still suffers from problems caused by some minimum voltages required by various devices or circuits. For example, field effect transistors, commonly used for various switching functions, require minimum gating voltages so as to function properly within favorable operating ranges. Similarly, some amplifier circuits, in order to provide sufficient output signal power, require higher power supply voltages.
Accordingly, many integrated circuit applications include charge pump circuits for amplifying, or multiplying, certain biasing or supply voltages. These charge pumps are powered by the normal power supply voltage VDD and typically operate in a two-stage switched mode of operation to provide a multiplied output voltage. In the initial phase of operation, a capacitor is charged to the level of the power supply voltage. Subsequently, during the next phase of operation, the circuit is switched such that the power supply voltage and charged capacitor voltage are connected in a serial arrangement to the output so as to create an elevated voltage. Such a charge pump is capable of providing as much as two times the power supply voltage VDD at its output terminal. Often, such charge pumps are used as power supplies for driving output capacitors.
While such charge pumps can provide increased voltages, the actual voltage available will vary depending upon the load conditions and power supply variations. For example, when the load is relatively large (i.e., a relatively large output, or load, current is required) and the power supply voltage (e.g., supplied by a battery) is relatively low, the multiplied voltage provided by the charge pump will become lower than desired. On the other hand, when the load is relatively small (i.e., the load current is relatively small) and the power supply voltage is relatively high (e.g., as can be true with a new set of batteries), the voltage provided by the charge pump may be too high, and thereby increase the possibility of inflicting damage upon some of the integrated circuit elements. Accordingly, accurate regulation of the charge pump output voltage is important.
One conventional technique of regulating a charge pump output voltage includes connecting a series of diodes to the charge pump output in a shunt connection, thereby preventing the output voltage from exceeding the maximum voltage defined by the sum of forward biased diode voltages. In the event that the charge pump output voltage becomes high enough to turn on the stack of diodes, output current is shunted through the diodes to circuit ground. However, for low power applications, such current drain is undesirable. Further, while this technique can prevent over-voltage conditions, it does not protect against under-voltage conditions.
Referring to FIG. 1, another conventional technique for regulating a charge pump output voltage relies upon the use of a controller 14 to control the clock generator 16 that drives the charge pump circuit 12. As discussed above, the power supply voltage 11 is multiplied by the charge pump 12 to produce the charge pump output voltage 13. This voltage 13 is monitored by the controller 14 which provides one or more appropriate control signals 15 to the clock generator 16. The clock generator 16, in turn, provides the appropriate differential clock signals 17 to drive the charge pump circuit 12.
Referring to FIG. 1A, these differential clock signals 17 include a non-inverted (xe2x80x9cpositivexe2x80x9d) 17p and inverted (xe2x80x9cnegativexe2x80x9d) 17n clock signal phases which are non-overlapping, i.e., with mutually exclusive asserted signal states.
One conventional implementation of this type 10 of regulated charge pump circuitry uses a controller 14 in which the charge pump voltage output voltage 13 is effectively sampled to provide the necessary control signals 15 for the clock generator 16 which, in turn, provides modulated clock signals 17 to drive the charge pump 12. While this has the beneficial effect of reducing current drain from the charge pump output 13, due to the sampling, such technique results in wasted power in the form of current drain through the sampled output since, during sampling, a large current from the charge pump output 13 becomes necessary since the sampling path must be of a low impedance so as to provide sufficient bandwidth for high frequency operation. (Further discussion of this type of regulated charge pump circuit can be found in U.S. Pat. No. 6,456,153, the contents of which are incorporated herein by reference.) For example, while increasing the impedance of the voltage sampling path will have the beneficial effect of reducing output current being shunted to ground, inherent parasitic capacitance associated with such current path, in conjunction with the high impedance, will substantially reduce the maximum operating speed of such sampling path.
Referring to FIG. 2, one conventional form 12a of the charge pump circuit 12 is a cross-coupled charge pump which includes N-type metal oxide semiconductor field effect transistors (N-MOSFETs) M15, M16, and P-type MOSFETs (P-MOSFETs) M13, M14, M17, M18, input coupling capacitors C1, C2, an output, or load, capacitor CLOAD, and an inherent parasitic capacitance CWELL between the power supply VDD terminal and the substrate well in which the transistors lie, all interconnected substantially as shown. Transistors M15 and M16 have their bulk regions connected to circuit ground, transistors M14, M17 have their bulk regions connected to the substrate well, as are the bulk regions and source terminals of P-MOSFETs M13 and M18. (Transistors M13 and M18 ensure that the substrate well is maintained at a voltage bias level sufficient to maintain output switching transistors M14 and M17 in their off states when reverse biased.) As can be seen, the N-MOSFETs are cross-coupled via their gate and source terminals, thereby providing automatic reverse bias of their respective gate-source junctions during switching by the differential input clock signal phases 17p, 17n. The switching of the outputs, so as to provide the voltage multiplication effect, as discussed above, is provided by P-MOSFETs M14, M17. (Further discussion of this charge pump circuit 12a can be found in Favrat et al., xe2x80x9cA High-Efficiency CMOS Voltage Doubler,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol. 33, No. 3, March 1998, the contents of which are incorporated herein by reference.)
In accordance with the presently claimed invention, an integrated charge pump circuit provides a regulated output voltage controlled by a voltage regulator with reduced power requirements in which the charge pump output voltage is a substantially constant multiple of the charge pump input voltage as defined by a voltage ratio which, in turn, is defined as a selected combination of a ratio of conductances of circuit elements within a feedback loop and ratios of other voltages including selected reference voltages and the charge pump input voltage.
In accordance with one embodiment of the presently claimed invention, an integrated charge pump circuit providing a regulated output voltage controlled by a voltage regulator with reduced power requirements includes terminals, output capacitance, charge pump circuitry, clock signal generator circuitry and control circuitry. An input power terminal conveys an input power voltage and an input power current. An input clock terminal conveys an input clock signal. The output capacitance responds to reception of the input power current by charging and providing an output power voltage. The charge pump circuitry, including first and second circuit branches and coupled to the input power terminal and the output capacitance, responds to reception of first and second clock signals with mutually exclusive signal assertion states by selectively conveying the input power current to the output capacitance alternately via the first and second circuit branches such that the output power voltage is a substantially constant multiple of the input power voltage as defined by an output ratio. The clock signal generator circuitry, coupled to the input clock terminal and the charge pump circuitry, responds to reception of the input clock signal and at least one control signal by providing the first and second clock signals. The control circuitry, coupled to the input power terminal, the input clock terminal, the output capacitance and the clock signal generator circuitry, responds to reception of first and second reference voltages, the input power voltage, the input clock signal and the output power voltage by providing the at least one control signal, and includes first and second pluralities of transistors having first and second conductances, respectively, responsive to the first and second reference voltages, the input power voltage and the output power voltage. A conductance ratio is defined by a ratio of the first and second conductances, a first input ratio is defined by a ratio of the first reference voltage and the input power voltage, a second input ratio is defined by a ratio of the second reference voltage and the input power voltage, and the output ratio is defined by a selected combination of the conductance ratio and the first and second input ratios.
In accordance with another embodiment of the presently claimed invention, an integrated charge pump circuit providing a regulated output voltage controlled by a voltage regulator with reduced power requirements includes terminals, output capacitance, a cross-coupled charge pump circuit, a latch circuit and a dynamic signal comparator circuit. An input power terminal conveys an input power voltage and an input power current. An input clock terminal conveys an input clock signal. The output capacitance responds to reception of the input power current by charging and providing an output power voltage. The cross-coupled charge pump circuit, including first and second cross-coupled circuit branches and coupled to the input power terminal and the output capacitance, responds to reception of first and second clock signals with mutually exclusive signal assertion states by selectively conveying the input power current to the output capacitance alternately via the first and second circuit branches such that the output power voltage is a substantially constant multiple of the input power voltage as defined by an output ratio. The latch circuit, coupled to the input clock terminal and the cross-coupled charge pump circuit, responds to reception of the input clock signal and first and second control signals by providing the first and second clock signals. The dynamic signal comparator circuit, coupled to the input power terminal, the input clock terminal and the output capacitance, responds to reception of first and second reference voltages, the input power voltage, the input clock signal and the output power voltage by providing the first and second control signals, and includes first and second pluralities of transistors having first and second conductances, respectively, responsive to the first and second reference voltages, the input power voltage and the output power voltage. A conductance ratio is defined by a ratio of the first and second conductances, a first input ratio is defined by a ratio of the first reference voltage and the input power voltage, a second input ratio is defined by a ratio of the second reference voltage and the input power voltage, and the output ratio is defined by a selected combination of the conductance ratio and the first and second input ratios.
In accordance with still another embodiment of the presently claimed invention, an integrated charge pump circuit providing a regulated output voltage controlled by a voltage regulator with reduced power requirements includes output capacitor means, charge pump means, clock signal generator means and controller means. The output capacitor means is for receiving an input power current and in response thereto charging and generating an output power voltage. The charge pump means is for receiving an input power voltage and first and second clock signals with mutually exclusive signal assertion states and in response thereto providing the input power current to the output capacitor means such that the output power voltage is a substantially constant multiple of the input power voltage as defined by an output ratio. The clock signal generator means is for receiving the input clock signal and at least one control signal and in response thereto generating the first and second clock signals. The controller means is for receiving first and second reference voltages, the input power voltage, the input clock signal and the output power voltage and in response thereto generating the at least one control signal with first and second controllable circuit means having first and second conductances, respectively, responsive to the first and second reference voltages, the input power voltage and the output power voltage. A conductance ratio is defined by a ratio of the first and second conductances, a first input ratio is defined by a ratio of the first reference voltage and the input power voltage, a second input ratio is defined by a ratio of the second reference voltage and the input power voltage, and the output ratio is defined by a selected combination of the conductance ratio and the first and second input ratios.